*Japanese*

Faculty Member

photo

Institute of Materials and Systems for Sustainability Center for Integrated Research of Future Electronics

NAKAMURA Tohru, Visiting Professor

E-Mail Address

nakamura.toru*@*b.mbox.nagoya-u.ac.jp(Please drop *'s before/after @ in sending e-mail.)

tohru*@*hosei.ac.jp(Please drop *'s before/after @ in sending e-mail.)

Academic Background

Work Experience

Academic Degree

03/1980 Doctor of Engineering

Keywords of Research themes

Advanced GaN &SiC transistors and applying them to analog circuits.

Ion implantation into GaN

Advanced double polysilicon high speed bipolar transistors

Academic Society Membership/Honors

1999-2005 Subcommittee member of research on III-V and V Devices in Society of Electron Devices, The Institute of Electrical Engineers of Japan
2001 Guest Editor, the Institute of Electrical and Electronics Engineers (IEEE) Transaction on Electron Devices
“Special Issue on Bipolar Transistor Technology, Vol. 48, No. 11”
1999 IEEE Fellow
“For contributions to the development of high-speed bipolar integrated circuits”
1997 Tokyo Governor’s Award - Distinguished Inventor
1997 – 2001 Subcommittee member of the IEEE Topical Workshop on Heterostructure Microelectronics
1993 – 1999 Editor for IEEE Transaction on Electron Devices
1991 Kanto Invention Award by Japan Institute of Invention and Innovation
1990 - 1992 Subcommittee member of the IEEE International Electron Devices Meeting (IEDM)

Original Papers

  1. GaN MISFETs Using Tilt Angle Ion Implantation of Magnesium, Hayao Kasai, Takuya Oikawa, Jun Kimura, Hiroki Ogawa, Tomoyoshi Mishima, Tohru Nakamura, IEEJ Transactions on Electronics, Information and Systems, Vol.136 No.4 pp.444-448 DOI: 10.1541/ieejeiss.136.444, 2016.
  2. Vertical GaN Diode with Field Plate Termination using High K Dielectric(Japanese), Michitaka Yoshino, Fumimasa Horikiri, Hiroshi Ohta, Yasuhiro Yamamoto, Tomoyoshi Mishima, Tohru Nakamura, IEEJ Transactions on Electronics, Information and Systems, Vol.136, No.4 pp.474–478 DOI: 10.1541/ieejeiss.136.474 , 2016
  3. 1.7 kV and 0.55 mΩ·cm2 GaN p-n Diodes on Bulk GaN Substrates with Avalanche Capability , K. Nomoto, B. Song, Z. Hu, M. Zhu, M. Qi, N. Kaneda, T. Mishima, T. Nakamura, D. Jena, H. Xing , IEEE Electron Device Letters , DOI .1109/LED.2015.2506638 , 2015.
  4. Vertical GaN p-n Junction Diodes With High Breakdown Voltages Over 4 kV , Hiroshi Ohta, Naoki Kaneda, Fumimasa Horikiri, Yoshinobu Narita, Takehiro Yoshida, Tomoyoshi Mishima and Tohru Nakamura , IEEE Electron Device Letters , Vol. 36, NO. 11, pp. 1180-1182 , 2015.
  5. Formation of definite GaN p-n junction by Mg-ion implantation to n—GaN epitaxial layers grown on a high-quality free-standing GaN substrate , Takuya Oikawa, Yusuke Saijyo, Shigeki Kato, Tomoyoshi Mishima, Tohru Nakamura , Nuclear Instruments and Methods in Physics Research B: Beam Interactions with Materials and Atoms , Vol. 365, Part A, pp.168-170 , 2015.
  6. A proposal to apply effective acceptor level for representing increased ionization ratio of Mg acceptors in extrinsically photon-recycled GaN , Kazuhiro Mochizuki, Tomoyoshi Mishima, Yuya Ishida, Yoshitomo Hatakeyama, Kazuki Nomoto, Naoki Kaneda, Tadayoshi Tsuchiya, Akihisa Terano, Tomonobu Tsuchiya, Hiroyuki Uchiyama, Shigehisa Tanaka and Tohru Nakamura , Materials Science Forum , Vols. 778-780 pp 1189-1192 , 2014.
  7. Nitrogen ion implantation isolation technology for normally-off GaN MISFETs on p-GaN substrate , Hayao Kasai, Hiroki Ogawa, Tomoaki Nishimura, Tohru Nakamura , Phys. Status Solidi (C) , 1–4 / DOI 10.1002/pssc.201300436 , 2014.
  8. Normally-off GaN MOSFETs with high-k dielectric CeO2 films deposited by RF sputtering , Hiroki Ogawa, Takuya Okazaki, Hayao Kasai, Kenta Hara, Yuki Notani, Yasuhiro Yamamoto and Tohru Nakamura , Phys. Status Solidi (C) , 1–5 / DOI 10.1002/pssc.201300314, 2014.
  9. High performance normally-off self-aligned metal gate GaN MISFETs on free-standing GaN substrates , Hiroki Ogawa, Hayao Kasai, Naoki Kaneda, Tomonobu Tsuchiya, Tomoyoshi Mishima and Tohru Nakamura , Phys. Status Solidi (C), 1–6 / DOI 10.1002/pssc.201300440, 2014.
  10. A 1/f Temperature Fluctuation Mechanism and Some Applications to Electronic Devices, Hisayuki Higuchi, Noriyuki Homma and Tohru Nakamura , Jap. J. Applied Physics, Jpn. J. Appl. Phys. , Vol. 52, pp. 104301-1-104301-8, DOI:10.7567/JJAP.52.104301, 2013.
  11. Determination of Lateral Extension of Extrinsic Photon Recycling in p-GaN by Using Transmission-Line-Model Patterns Formed with GaN p-n Junction Epitaxial Layers , Kazuhiro Mochizuki, Tomoyoshi Mishima, Yuya Ishida, Yoshitomo Hatakeyama, Kazuki Nomoto, Naoki Kaneda, Tadayoshi Tshuchiya, Akihisa Terano, Tomonobu Tsuchiya, Hiroyuki Uchiyama, Shigehisa Tanaka, Tohru Nakamura , Jpn. J. Appl. Phys , Vol. 52, No. 8, DOI:10.7567/JJAP.52.08JN22, 2013.
  12. High transconductance ion-implanted GaN MISFETs using atomic layer deposited high-k dielectrics , S. Gu, H. Katayose, K. Nomoto, T. Nakamura, A. Ohoka, K. Lee, W. Lu, P. M. Asbeck , Physics Status Solidi C , Vol. 10, No. 5, pp. 820-823, DOI: 10.1002/pssc.201200625 , 2013.
  13. High-Breakdown-Voltage and Low-Specific-on-Resistance GaN p–n Junction Diodes on Free-Standing GaN Substrates Fabricated Through Low-Damage Field-Plate Process , Yoshitomo Hatakeyama, Kazuki Nomoto, Akihisa Terano, Naoki Kaneda, Tadayoshi Tsuchiya, Tomoyoshi Mishima and Tohru Nakamura , Japanese Journal of Applied Physics , Vol. 52, 28007, pp. 1-3 , 2013.
  14. Influence of Surface Recombination on Forward Current Voltage Characteristics of Mesa GaN p+n Diodes Formed on GaN Free-Standing Substrates , K. Mochizuki, K. Nomoto, Y. Hatakeyama, H. Katayose, T. Mishima, N. Kaneda, T. Tsuchiya, A. Terano, T. Ishigaki, T. Tsuchiya, R. Tsuchiya, and T. Nakamura , IEEE Trans. Electron Devices , Vol. 59, No.4, pp.1091-1097 , 2012.
  15. Effects of Surface Micromesas on Reverse Leakage Current in InGaN/GaN Schottky Barriers , W. Lu, T. Nishimura, L Wang, T. Nakamura, P.Yu and P. Asbeck , J. Applied Physics , 112, 44505(1-9) , 2012.
  16. Over 1.0 kV GaN p-n Junction Diodes on Free-Standing Substrates , Kazuki Nomoto, Yoshitomo Hatakeyama, Hideo Katayos, Tohru Nakamura, Naoki Kaneda and Tomoyoshi Mishima , Physica Status Solidi(A) , Vol. 208 , 2012.
  17. High Threshold Voltage Normally-Off GaN MISFETs Using Self-Alignment Technique , Shinya Taguchi, Kazuya Hasegawa, Kazuki Nomoto and Tohru Nakamura , Physica Status Solidi(C) , Vol. 9, Issue 3-4, PP.858-860 , 2012.
  18. Over 3.0 GW/cm2 Figure-of-Merit GaN p-n Junction Diodes on Free-Standing GaN Substrates , Yoshitomo Hatakeyama, Kazuki Nomoto, Naoki Kaneda, Toshihiro Kawano, Tomoyoshi Mishima, Senior Member, IEEE, and Tohru Nakamura , IEEE Electron Devices Letters , Vol.32, No.12, pp.1674-1676 , 2011.
  19. 55nm Gate Ion-Implanted GaN HEMTs on Sapphire and Si Substrates , Hideo Katayose, Masanao Ohta, Kazuki Nomoto, Norio Onojima, Tohru Nakamura , Physica Status Solidi(C), pp. 1- 3 /DOI 10.1002/pssc.201001018 , 2011.
  20. Self-Aligned Silicide Gate GaN MISFET with Normally-Off operation , Shinya Taguchi, Kazuya Hasegawa, Kazuki Nomoto and Tohru Nakamura , Physica Status Solidi(C) , pp. 1– 3 /DOI10.1002/pssc.201001018 , 2011.
  21. Over 1.0 kV GaN p-n Junction Diodes on Free-Standing Substrates , Kazuki Nomoto, Yoshitomo Hatakeyama, Hideo Katayos, Tohru Nakamura, Naoki Kaneda and Tomoyoshi Mishima , Physica Status Solidi(A) , Vol. 208, Issue 7/2011, page 1535-1537 , 2011.
  22. Characterization of silicon ion-implanted GaN and AlGaN , Kazuki Nomoto, Yuki Toyoda, Masataka Satoh, Taroh Inada, Tohru Nakamura , Nuclear Instruments and Methods in Physics Research B , 2011.
  23. High-temperature operation of GaN based OPAMP on silicon substrate , Kazuki Nomoto, Kazuya Hasegawa, and Tohru Nakamura , High-temperature operation of GaN based OPAMP on silicon substrate , Physica Status Solidi C 7-8, 1952-1954 , 2010.
  24. Impact of C Ion Irradiation on Chemical and Electrical Properties of Pentacene Organic Film , Tomohisa Yabe, Yuuki Sakamoto, Tomoaki Nishimura, and Masataka Satoh , Ion Beam Modification of Materials , 535 , 2010年
  25. Improvement of Current Gain in Triple Ion Implanted 4H-SiC Bipolar Junction Transistor with Etched Extrinsic Base Regions, T. Tajima, T. Nakamura, M. Satoh and T. Nakamura, IEEJ Transactions on Electronics, Information and Systems, Vol. 130, No. 12, PP. 2188-2191,2010 , 2010.
  26. Reduction of On-Resistance in Ion-Implabnted GaM/AlGaN/GaN HEMTs with Low Gate Leakage Current, Kazuki Nomoto, Masataka Satoh and Tohru Nakamura, IEEJ Transactions on Electronics, Information and Systems, Vol. 128-C, No.6, pp. 885-889 , 2008.
  27. Low-Frequency Noise Characteristics in Ion-Implanted GaN-Based HEMTs , M. Nakajima, T. Ohsawa, K. Nomoto, and T. Nakamura , IEEE Electron Devices Letters , Vol. 29, No. 8, pp.827-829 , 2008.
  28. Remarkable Reduction of On-Resistance by Ion Implantation in GaN/AlGaN/GaN HEMTs With Low Gate Leakage Current , K. Nomoto, T. Tajima, T. Mishima, M. Satoh, and T. Nakamura , IEEE Electron Devices Letters , Vol. 28, No. 11, pp. 939-941 , 2007.
  29. Si+ Implanted AlGaN/GaN HEMTs with Reduced On-Resistance , K. Nomoto, T. Mishima, M. Satoh, and T. Nakamura , Phys. Stat. Sol. (c) 4 , pp. 2704-2707 , 2007.
  30. Impact of Si+ Implantation on Reduction of Contact Resistance in Ti/Al contact to GaN , M. Satoh, N. Itoh, K. Nomoto, T. Nakamura, and T. Mishima , Phys. Stat. Sol. (c) 4 , pp. 2621-2624 , 2007.
  31. 1/f noise characteristics of sub-0.1micron CMOS for high-speed analog ULSI , T. Nakamura, M. Hase, K. Ohnishi, R. Tuchiya and T. Onai , Physics of Semiconductor Devices II, 2004 Narosa Publishing House , pp. 774-778 , 2003.
  32. High-Speed Small-Scale InGaP/GaAs HBT Technology and Its Application to Integrated Circuits , T. Oka, K. Hirata, H. Suzuki, K. Ouchi, H. Uchiyama, T. Taniguchi, K. Mochzuki, and T. Nakamura , IEEE Transaction on Electron Devices , Vol. ED-48, No. 11, pp. 2625-22630 , 2001.
  33. Bipolar Transistor Technology: Past and Future Directions , P. M. Asbeck and T. Nakamura , IEEE Transaction on Electron Devices , Vol. ED-48, No. 11, pp. 2455-2456 , 2001.
  34. Small-Scale InGaP/GaAs Heterojunction Bipolar Transistors for High-Speed and Low Power Integrated Circuit Application, T. Oka, K. Hirata, H. Suzuki, K. Ouchi, H. Uchiyama, T. Taniguchi, K. Mochizuki and T. Nakamura, International J. High Speed Electronics & Systems, Vol. 11, No.1, 2001.
  35. Linearity Study on Enhance/Depletion Dual-Gate High Electron Mobility Transistors Using Gain Mapping Method, T. Tanimoto, A. Kawai, I. Ohbu, H. Takazawa and T.,Nakamura, Jpn. J. Jppl. Phys.Vol. 38, Part1, No. 7A, pp. 3972-3975, 1999年
  36. Small-Scaled InGaP/GaAs HBTs with WSi/Ti Base Electrode and Buried SiO2, T.Oka, K. Hirata, K. Ouchi, H. Uchiyama, T. Taniguchi, and T. Nakamura, IEEE Transaction on Electron Devices vol. ED-45, No. 11, pp. 2276-2282, 1998.
  37. InGaP/GaAs HBTs with High-Speed and Low-Current Operation Fabricated Using Submicron Self-Aligned HBT’s by Selective Emitter Growth, S. H. Park, T. P. Chin, Q. Z. Liu, S. L. Fu, T. Nakamura, P. K. L. Yu and P. M. Asbeck, IEEE Electron Device Letters vol. 19, No. 4, pp.118-120, 1998.
  38. Experimentally Proven Equation for the Collector-Depletion-Layer Transit Time of npn Bipolar Transistors, K. Mochizuki, T. Uchino and T. Nakamura, Jpn. J. Jppl. Phys.Vol. 36, Part1, No. 11, pp.6724-6725, 1998.
  39. High-Speed InGaP/GaAs Transistors with a Sidewall Base Contact Structure, K. Mochizuki, T. Tanoue, T. Oka, K. Ouchi, K. Hirata and T. Nakamura, IEEE Electron Device Letters vol. 18, No. 11, pp. 562-564, 1997.
  40. Molecular Beam Deposition of n-type Polycrystaline InGaAs for High Resistances in Heterojunction Bipolar Transistor Integrated Circuits, K. Mochizuki, T. Oka and T. Nakamura, Electronics Letters vol. 33, No. 13, p. 1181, 1997.
  41. High Speed InGaP/GaAs Heterojunction Bipolar Transistors with Buried SiO2 Using WSi as the Base Electrode, T. Oka, K. Ouchi, H. Uchiyama, T. Taniguchi, K. Mochizuki and T. Nakamura, IEEE Electron Device Letters vol. 18, No. 4, pp. 154-156, 1997.  
  42. A WSi Base Electrode and a Heavily-Doped Thin Base Layer for High-Speed and Low-Power InGaP/GaAs HBTs, Oka, K. Ouchi, K. Mochizuki and T. Nakamura, Japanese J. Applied Physics vol. 36, No. 3B, pp. 1804-1806, 1997.
  43. Small InGaP/GaAs Heterojunction Bipolar Transistors with High-Speed Operation, (T. Oka, K. Ouchi and T. Nakamura, Electronics Letters vol. 33, No. 4, pp. 339-340, 1997.
  44. A Very Small Bipolar Transistor Technology with Sidewall Polycide Base Electrode for ECL-CMOS LSI, T. Shiba, Y. Tamaki, T. Onai, Y. Kiyota, T. Kure and T. Nakamura, IEEE Transaction on Electron Devices vol. ED-43, No. 9, pp. 1357-1363, 1996.
  45. Double-layer μC-Si/a-SiCx Emitter in a Silicon Heterojunction Bipolar Transistor with a Cutoff-Frequency of 47 GHz, M. Kondo, T. Shiba, Y. Tamaki, and T. Nakamura, Journal of Electrochemical Society vol. 143, No. 6, pp. 1949-1955, 1996.
  46. Shallow p-Type Layers in Si by Rapid Vapor-Phase Doping for High-Speed Bipolar and MOS Applications, Y. Kiyota, T. Nakamura, S. Suzuki and T. Inada, IEICE Transaction on Electronics vol. E79-C, No.4, pp. 554-559, 1996.
  47. AlGaAs/GaAs HBTs with buried SiO2 in the Extrinsic Collector, K. Mochizuki, T. Nakamura, T. Tanoue and H. Masuda, Solid-State Electronics vol. 38, No. 9, pp. 1619-1622, 1995.
  48. Process and Device Technology for High-Speed Self-Aligned Bipolar Transistor(Invited Paper), T. Nakamura, T. Shiba, T. Onai, T. Uchino, Y. Kiyota, K. Washio and N. Homma, IEICE Transaction on Electronics vol. E78-C, No.9, pp. 1154-1164, 1995.
  49. Behavior of Active and Inactive Boron in Si Produced by Vapor-Phase Doping during Subsequent hydrogen Annealing,, Y. Kiyota, T. Nakamura, K. Muraki, H. Niwamura and T. Inada, Japanese journal of Applied Physics vol. 34, No. 6, pp. 2981-2985, 1995.
  50. High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSI’s, K. Washio, H. Shimamoto and T. Nakamura, IEICE Transaction on Electronics vol. E78-C, No.4, pp. 353-359, 1995.
  51. Recent Progress in Bipolar Transistor Technology(Invited Paper), T. Nakamura, H. Nishizawa, IEEE Transaction on Electron Devices, vol. ED-42, No. 3, pp. 390-398, 1995.
  52. Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSIs, T. Onai, E. Ohue, Y. Idei, M. Tanabe, H. Shimamoto, K. Washio and T. Nakamura, IEEE Transaction on Electron Devices vol. ED-42, No. 3, pp. 413-418, 1995.
  53. Selective-Area Epitaxy of Carbon-Doped AlGaAs by Chemical Beam Epitaxy, T. Y. Li, H. K. Dong, Y. M. Hsin, P. M. Asbeck, C. W. Tu and T. Nakamura, Journal of Vacuum Science Technology B, vol. 13, No. 2, pp. 664-666, 1995.
  54. Fully Radiative Current Path Structure (FRACS) for Sub-0.1 μm Emitter Transistor, T. Onai, K. Nakazato, Y. Kiyota, and T. Nakamura, IEEE Transaction on Electron Devices vol. ED-42, No. 1, pp. 23-30, 1995.
  55. Boron -Doping in Si Using Atmospheric Pressure CVD, Y. Kiyota, T. Nakamura and T. Inada, Applied Surface Science 82/83, pp. 400-404, 1994.
  56. Phosphorus Direct Doping from Vapor Phase into Silicon for Shallow Junctions, Y. Kiyota, T. Nakamura, K. Muraki and T. Inada, Journal of Electrochemical Society vol. 141, No. 8, pp. 2241-2244, 1994.
  57. Comparison of Be and C Diffusion in Heavily Doped Polycrystalline GaAs, K. Mochizuki and T. Nakamura, Applied Physics Letters vol. 65, No.16, pp. 2066-2068, 1994.
  58. Molecular Beam Deposition of Low Resistance Polycrystalline GaAs, K. Mochizuki, T. Nakamura, T. Mishima, H. Masuda and T. Tanoue, Journal of Electronic Materials vol. 23, No. 6, pp. 577-580, 1994.
  59. A New Test Structure for the Evaluation of Graft-Base Lateral Diffusion Depth in High Performance Bipolar Transistors, Y. Tamaki, T. Shiba, T. Kure and T. Nakamura, IEEE Transaction on Semiconductor Manufacturing vol. 7, No. 3, pp. 279-283, 1994.
  60. Sub-quarter Micrometer PMOSFETs with 50 nm Source and Drain Formed by Rapid Vapor, Y. Kiyota, T. Nakamura and T. Inada, IEICE Transaction on Electronics vol. E77-C, No.3, pp. 362-366, 1994.
  61. A 64 GHz fT and 3.6 VBVCEO Si Bipolar Transistor Using inSitu Phosphorus-Doped and Large-Grained Polysilicon Emitter Contacts, M. Nanba, T. Uchino, M. Kondo, T. Nakamura, T. Kobayashi, Tamaki and M. Tanabe, IEEE Transaction on Electron Devices vol. ED-40, No. 8, pp. 1563-1565, 1993.
  62. Characteristics of Shallow Boron-Doped Layers in Si by Rapid Vapor-Phase Direct Doping, Y. Kiyota, T. Nakamura, T. Inada, A. Kuranouchi and Y. Hirano, Journal of Electrochemical Society vol. 140, No. 4, pp. 1117-1121, 1993.
  63. SEPIA: A New Isolation Structure for Soft-Error-Immune LSI’s, T. Onai, T. Nakamura and N. Homma, IEEE Transaction on ElectronDevicesVol.ED-40, No.2, pp. 402-406, 1993.
  64. Soft-Error-Immune 180μm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAM, Y. Idei, T.Shiba, T. Nakamura, T. Onai, Y. Tamaki, N. Homma, K. Yamaguchi and Y. Sakura, IEICE Transaction on Electronics vol. E75-C, No.11, pp. 1369-1376, 1992.
  65. Ultra-Thin-Base Si Bipolar Transistor Using Rapid Vapor-Phase Direct Doping, Y. Kiyota, T. Onai, T. Nakamura, T. Inada, A. Kuranouchi and Y. Hirano, IEEE Transaction on ElectronDevicesVol.ED-39, No.9, pp. 2077-2081, 1992.
  66. Considerations of Ultrahigh-Speed Low-Power Active Pull Down NTL Logic Circuits, M.Usami, T. Nakamura, N. Shiozawa, M. Tanabe and T. Mandai, Electronics and Communication in Japan Part 2(Electronics) vol.75, No. 8, pp. 72-82, 1992.
  67. Advanced Process Device Technology for 0.3μm High-Performance Bipolar LSI's, Tamaki, T. Shiba, T. Kure, K. Ohyu, and T. Nakamura, IEEE Transaction on ElectronDevicesVol.ED-39, No.6¸IEEE TransactiononElectronDevicesVol.ED-39, No.6, pp.1387-1391, 1992.
  68. 0.5μm Very-High-Speed Silicon Bipolar Device Technology - U-Groove Isolated SICOS, T. Shiba, Y. Tamaki, T. Kure, T. Kobayashi and T. Nakamura, IEEE Transaction on Electron Devices Vol. ED-38, No. 11, pp.2505-2511, 1991.
  69. Formation of Ultra-shallow P+ Layers in Silicon by Thermal Diffusion of Boron and by Subsequent Rapid Thermal Annealing, T. Inada, A. Kuranouchi, H. Hirano, T. Nakamura, Y. Kiyota and T. Onai, Applied Physics Letters,Vol.58, No.16, pp. 1748-1750, 1991.
  70. Structural Dependence on Device Characteristics for Sidewall Base Contact Structure,  K. Washio, K. Nakazato and T. Nakamura,  Electronics and Communication in Japan Part 2(Electronics)vol. 73, No. 5, pp. 181-190, 1990.
  71. Base Peripheral Effects on High Performance Self-Aligned Bipolar Device(SICOS), T. Shiba, Y. Tamaki, T. Nakamura, M. Nanba and K. Ikeda, Electronics and Communication in Japan Part 2(Electronics)vol. 73, No. 5,  pp. 100-105, 1990.
  72. An Experimental Soft-error-immune 64-Kbit3-ns ECL Bipolar RAM, K. Yamaguchi, H. Nambu, K. Kanetani, N. Homma, T. Nakamura, K. Ohhata, A. Uchida, K. Ogiue, IEEE Journal of Solid-State Circuits Vol.SSC-24, No.5, pp. 1390-1396, 1989.
  73. Process Design of a Novel Shielded SBD and Its Device Characteristics, K. Sagara, T. Onai, N. Homma and T. Nakamura, IEEE Transaction on ElectronDevicesVol.ED-36, No.9, pp. 1853-1854, 1989.
  74. A Novel CMOS Structure with a Reduced Drain-Substrate Capacitance, K. Sagara and T. Nakamura, IEEE Transaction on Electron Devices vol. 36, No. 3, pp. 598-600, 1989.
  75. Soft-error-immune Switched-load-resistor Memory Cell, N. Homma, T. Nakamura, T. Hayashida, M. Matsumoto, K. Nakazato, T. Onai, Y. Tamaki, M. Namba, K. Sagara and K. Ikeda, IEEE Transaction on Electron Devices Vol.35, No.12, pp.2094-2100, 1988.
  76. Fabrication Process and Device Characteristics of Sidewall Base Contact Structure Transistor Using Two-Step Oxidation of Sidewall Surface, K. Washio, T. Nakamura and T. Hayashida, IEEE Transaction on Electron Devices Vol.35, No.10, pp.1596-1600, 1988.
  77. An Analysis and Experimental Investigation of the cutoff Frequency fT of High-speed Bipolar Transistors, M. Nanba, T. Shiba, T. Nakamura and T. Toyabe, IEEE Transactions on Electron Devices Vol. ED-35, No.7, pp.1021-1028, 1988.
  78. The Effect of Thin Interfacial Oxides on the Electrical Characteristics of Silicon Bipolar Device, K. Sagara, T. Nakamura, Y. Tamaki and T. Shiba, IEEE Transactions on Electron Devices Vol. ED-34, No.11, pp.2286-2290, 1987.
  79. 2.7ns 8x8-bit Parallel Array Multiplier Using Sidewall Base Contact Structure, K. Washio, K. Nakazato and T. Nakamura, IEEE Journal of Solid-sate CircuitsVol.SC-22, No.4, pp. 613-614, 1987.
  80. Wideband Monolithic AGC AMP for 400 Mbit/s Optical Repeaters Using Advanced Si Bipolar IC Technology, SICOS, T. Kinoshita, K. Yamashita, M. Maeda and T. Nakamura, Electronics Letters vol. 22, No. 4, pp.188-189, 1986.
  81. Hole Spreading Effect on Upward Current Gain in NPN Transistor, K. Nakazato and T. Nakamura, IEEE Transaction on Electron Devices Vol. ED-32, No5, pp. 965-971, 1985.
  82. Characteristics and Scaling Properties of NPN Transistors with Sidewall Base Contact Structure, K. Nakazato, T. Nakamura, T. Okabe and M. Nagata, IEEE Journal of Solid-Sate Circuits vol. SC-20, No. 1, pp. 248-252, 1985.
  83. High Speed IIL Circuits Using Side-wall Base Contact Structure, T. Nakamura, K. Nakazato, T. Miyazaki, T. Okabe and M. Nagata, IEEE Journal of Solid-Sate Circuits vol. SC-20, No. 1, pp. 168-172, 1985.
  84. Degradation Analysis of Lateral PNP Transistor Exposed to X-Ray Irradiation, M. Kato, T. Nakamura, T. Toyabe, T. Okabe and M. Nagata, IEEE Transaction on Nuclear Sciencev ol. NS-31, No. 6, pp.1513-1517, 1984.
  85. Self-Aligned Transistor with Sidewall Base Electrode, T. Nakamura, T. Miyazaki, S. Takahashi, T. Kure, T. Okabe and M. Nagata, IEEE Transaction on Electron Devices vol. ED-29, No, 4, pp. 596-600, 1982.
  86. Silicon Bipolar Transistors Fabricated Using Ion Implantation and Laser Annealing, N. Natsuaki, T. Miyazaki, M. Ohkura, T. Nakamura, M. Tamura and T. Tokuyama, Laser and Electron Beam Solid Interactions and Materials Processing, pp. 375-380, 1980.
  87. Photocurrent-Driven B-MOS without External Power Supply, T. Nakamura, T. Masuhara and S. Asai, Japan, J. Appl. Phys .Vol. 17, Suppl. 17-1, pp.43-47, 1977.
  88. Low Temperature Silicon Epitaxy by Partially Ionized Vapor Deposition, T. Itoh, T. Nakamura, M. Muromochi and T. Sugiyama, Japan. J. Applied Physics vol. 16、No. 4, pp. 553-557, 1977.
  89. Antimony Concentration in Silicon Epitaxial Layer Formed by Partially Ionized Vapor Deposition, T. Itoh, T. Nakamura, M. Muromochi and T. Sugiyama, Japan. J. Applied Physics vol. 15、No. 6, pp. 1145-1146, 1977.
  90. Epitaxial Growth of Silicon Assisted byIon Implantation, T. Itoh and T. Nakamura, Radiation Effects Vol. 9, pp. 1-4, 1971.
  91. Analysis of Carrier Transport in Vacuum Evaporated Epitaxial Films of Silicon on Spinel, S. Hasegawa, N. Kaminaka, T. Nakamura and T. Itoh, Journal of Applied Physics vol. 40, No. 11, pp. 4620-4623, 1969.

Presentations

  1. GaN-on-GaN p-n Power Diodes with 3.48 kV and 0.95 mΩ·cm2: A Record High Figure-of-Merit of 12.8 GW/cm2, K. Nomoto, M. Zhu, B. Song, Z. Hu, M. Qi, R. Yan, V. Protasenko, E. Imhoff, J. Kuo, N. Kaneda, T. Mishima, T. Nakamura , International Electron Devices Meeting, (Power and Compound Semiconductor Devices Advanced Compound RF and Power Devices 9.7) , Washington DC , 2015.
  2. P‐type Graphene on Ion‐Implanted 4H‐SiC by CF4 Plasma Treatment , Yusuke Shiina, Tomoaki Nishimura, Tohru Nakamura , International Conference on Silicon Carbide and Related Materials 2015 , Th‐P‐57 , 2015.
  3. CeO2 Dielectrics Passivation for GaN Diode with a Field Plate Termination, Michitaka Yoshino, Fumimasa Horikiri, Hiroshi Ohta, Tomonari Furuya, Tomoyoshi Mishima, Yasuhiro Yamamoto, Tohru Nakamura , E-MRS 2015 Fall Meeting, Symposium H (Invited) , 9-3, 2015.
  4. High-breakdown-voltage and low-on-resistance GaN p-n junction diodes on free-standing GaN substrates , Yohei Otoki, Masatomo Shibata, Hitachi Metals, Kazuki Nomoto, Akihisa Terano, Naoki Kaneda, Tomoyoshi Mishima, Tohru Nakamura , SPIE Photonics West 2015, Gallium Nitride Materials and Devices X , 9363-41 , 2015.
  5. Evaluation of highly Mg-ion-implanted GaN layers grown on free-standing GaN substrates , Y. Saijo, H. Tsuge, S. Kato, T. Oikawa, T. Nishimura, T. Mishima, T. Nakamura , 22nd International Conference on Ion Beam Analysis, IBA2015-Book-of Abstracts-0612 PB-33 , 2015.
  6. Evaluation of GaN Epitaxial Layers Grown on Free-Standing GaN Substrates by Fabrications of p-n Diodes, Tomoyoshi Mishima, Kazuki Nomoto and Tohru Nakamura, 2015 MRS Spring Meeting , DD6.11, CC2.01 , 2015.
  7. Formation of definite GaN p-n junction by Mg-ion implantation to n--GaN epitaxial layers grown on a high-quality free-standing GaN substrate , Takuya Oikawa, Yusuke Saijo, Shigeki Kato, Tomoyoshi Mishima, Tohru Nakamura, 19th International Conference on Ion Beam Modification of Materials(IBMM2014) , PC86 , 2014.
  8. Threshold Voltage Control of GaN MISFETs Using Tilt Angle Ion Implantation of Magnesium, Hayao Kasai, Takuya Oikawa, Hiroki Ogawa, Tomoyoshi Mishima and Tohru Nakamura , International Workshop on Nitride Semiconductor 2014 (IWN2014) , WeEP12 , 2014.
  9. Graphene Grown on Ion-Implanted 4H-SiC and an Effect of Pre-Plasma Treatment , Toru Sugimachi, Yusuke Shiina, Daiki Aoyagi, Tomoaki Nishimura, Tohru Nakamura , Proc.of 2014 MRS Spring Meeting , DD6.11, 2014 San Francisco, Paper Number:1878188.0 , 2014年
  10. Nitrogen Ion Implantation Isolation Technology for Normally-GaN MISFETs on p-GaN Substrate , Hayao Kasai, Hiroki Ogawa, Tomoaki Nishimura, Tohru Nakamura , 10th Internatinal Conference on Nitride Semiconductors 2013 PROGRAM & EXHIBIT GUIDE , P261, DP2.22, 2013.
  11. High Performance Normally-off Self-aligned Metal Gate GaN MISFETs on Free Standing GaN Substrates, Hiroki Ogawa, Hayao Kasai, Tomonobu Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima, Tohru Nakamura , 2013 ICNS-10 10th International Conference on Nitride Semiconductors 2013 PROGRAM & EXHIBIT GUIDE , P262, DP2.23 , 2013.
  12. Normally-off GaN MOSFETs with High-k Dielectric CeO2 Films Deposited by RF Sputtering, H. Ogawa, T. Okazaki, H. Kasai, K. Hara, Y. Notani, Y. Yamamoto and T. Nakamura , E-MRS 2013 SPRING MEETING , L-2, L-24 , 2013.
  13. High Transconductance Ion-Implanted GaN MISFETs Using Atomic Layer Deposited High- κ Dielectrics , S. Gu, A. Ohoka, K. Lee, W. Lu, P. M. Asbeck, H. Katayose, K. Nomoto, T. Nakamura , 39th International Symposium on Compound Semiconductors , Mo-P.37 , 2012年
  14. Photon-recycling GaN p-n Diodes Demonstrating Temperature-independent, Extremely Low On-resistance , K. Mochizuki, K. Nomoto, Y. Hatakeyama, H. Katayose, T. Mishima, N. Kaneda, T. Tsuchiya, A. Terano, T. Ishigaki, T. Tsuchiya, R. Tsuchiya, and T. Nakamura , IEDM Digest of Technical Papers , IEDM11-591-594 , 2011.
  15. Large GaN p-n Junction Diodes of 3 mm in Diameter on Free-Standing GaN Substrates with High Breakdown Voltage, Kazuki Nomoto, Tohru Nakamura, Naoki Kaneda, Toshihiro Kawano, Tadayoshi Tsuchiya and Tomoyoshi Mishima , Abstract at International Conference on Silicon Carbide and Related Materials held at Cleveland , Ohio , 2011.
  16. High Threshold Voltage Normally-Off GaN MISFETs Using Self-Alignment Technique , Shinya Taguchi, Kazuya Hasegawa, Kazuki Nomoto and Tohru Nakamura , 9th International Conference on Nitride Semiconductors , PI2.10 , 2011.
  17. 55nm Gate Ion-Implanted GaN HEMTs on Sapphire and Si Substrates , Hideo Katayose, Masanao Ohta, Kazuki Nomoto, Norio Onojima, Tohru Nakamura , International Workshop on Nitride semiconductors (IWN2010), IWN2010 PROGRAM&ABSTRACTS , IP1.17, P.243,No. 7–8, 1952–1954 , 2010.
  18. Self-Aligned Silicide Gate GaN MISFET with Normally-Off operation, Shinya Taguchi, Kazuya Hasegawa, Kazuki Nomoto and Tohru Nakamura , International Workshop on Nitride semiconductors (IWN2010), IWN2010 PROGRAM&ABSTRACTS , IP1.6, P.240 , 2010.
  19. Over 1.0 kV GaN p-n Junction Diodes on Free-Standing Substrates , Kazuki Nomoto, Yoshitomo Hatakeyama, Hideo Katayos, Tohru Nakamura, Naoki Kaneda and Tomoyoshi Mishima , International Workshop on Nitride semiconductors (IWN2010), IWN2010 PROGRAM&ABSTRACTS , 2010.
  20. Impact of CF4 Plasma Treatment on the Surface Roughness of Ion Implanted SiC Induced by High Temperature Annealing , T. Sugimoto, M. Satoh, T. Nakamura, K. Mashimo, H. Doi and M. Shibagaki , Materials Science Forum Vols. 645-648 , pp 783-786 , 2010.
  21. Improvement of current gain with etched extrinsic base regions of triple ion implanted SiC BJT , T. Tajima, T. Nakamura, Y. Watabe, M. Satoh, T. Nakamura , Materials Science Forum Vols. 645-648 , pp 1065-1067 , 2010.
  22. Ion Implantation into GaN & Advanced GaN HEMT Devices , Tohru Nakamura , Special Lecture Program for Distinguished Foreign Scholar at Hangyang University, Seoul, Korea , Nov. 4 , 2009年11.
  23. Multiple ion-implanted GaN/AlGaN/GaN HEMTs with remarkably low parasitic source resistance , K. Nomoto, M. Satoh, and T. Nakamura , Materials Science Forum Vols. 600-603 , pp. 1325-1328 , 2009.
  24. Reliability of High-Temperature Operation for GaN-Based Operational Amplifiers , Kazuki Nomoto, Kazuya Hasegawa, Masataka Satoh and Tohru Nakamura , Material Research Society Fall Meeting 2009 , B8.2 , 2009.
  25. High Current Gain Triple Ion Implanted 4H-SiC BJT , Taku Tajima, Tadashi Nakamura, Yuki Watabe, Masataka Satoh and T. Nakamura , Material Research Society Fall Meeting 2009 , B8.3 , 2009.
  26. Degradation of Current Gain for Ion Implanted 4H-SiC Bipolar Junction Transistor, Yuki Watabe, Taku Tajima, and T. Nakamura, Material Research Society Fall Meeting 2009 , B8.4 , 2009.
  27. Improvement of Current Gain with Etched Extrinsic Base Regions of Triple Ion Implanted SiC BJT , Taku Tajima, Tadashi Nakamura, Yuki Watabe, Masataka Satoh and T. Nakamura , International Conference Silicon Carbide and Related Materials 2009 , We-P-70, II-132 , 2009.
  28. High-Temperature Operation of GaN-Based OPAMP on Silicon Substrate , Kazuki Nomoto, Kazuya Hasegawa, and Tohru Nakamura , 8th International Conference on Nitride Semiconductors , P1701 , 2009.
  29. RBS and electrical characterization of Ti/Al-based ohmic contacts to n-GaN , Kazuki Nomoto, Nobuyuki Ito, Taroh Inada, Masataka Satoh, and Tohru Nakamura , 19th Ion Beam Analysis , Tu050 , 2009.
  30. Self-Aligned Ion-Implanted GaN MISFETs , Kazuki Nomoto, Kazuya Hasegawa, Masanao Ohta, Taku Tajima and Tohru Nakamura , 2009 Topical Workshop on Heterostructure, WeA-9 , 2009.
  31. Integrated GaN/AlGaN/GaN HEMTs with Preciously Controlled Resistance on Silicon Substrate Fabricated by Ion Implantation, K. Nomoto, T. Ohsawa, M. Satoh, and T. Nakamura , Mater. Res. Soc. Symp. , Proc. Vol. 1068, 1068-C03-06 , 2008
  32. Structural and electrical properties of poly-3C-SiC layer grown from P ion implanted 4H-SiC , M. Satoh, T. Jinushi, and T. Nakamura, , The 7th European Confrence on Silicon Carbide and Related Materials , TuP-55 , 2008.
  33. Doping level dependence of electrical properties for p+n 4H-SiC diode formed byAl ion implantation , M. Satoh, S. Nagata, T. Nakamura, H. Doi, M. Shibagaki, , Doping level dependence of electrical properties for p+n 4H-SiC diode formed byAl ion implantation , MoP-54 , 2008.
  34. Impact of initial implantation damage on electrical activation process of on implanted N in 4H-SiC(0001) , M. Satoh, T. Kudoh, and T. Nakamura , The 16th Int. Conf. Ion Beam Modification of Materials , PA-0413 , 2008.
  35. Ohmic contacts on n-type layers formed in GaN/AlGaN/GaN by dual-energy Si ion implantation , T. Shiino, T. Saitoh, T. Nakamura, T. Inada, , The 16th Int. Conf. Ion Beam Modification of Materials , PA-05-10 , 2008.
  36. Effect of base impurity concentration on DC charateristics of double ion implanted 4H-SiC BJTs , T. Tajima, S. Uchiumi, K. Tsukamot, K. Takenaka, M. Satoh, and T. Nakamura , Mater. Res. Soc. Symp. , Proc. 1069, 1069-D01-20 , 2008.
  37. Effect of Base Impurity Concentration on DC Characteristics of Double Ion Implanted 4H-SiC BJTs, T. Tajima, S. Uchiumi, K. Tsukamoto, K. Takenaka , MRS 2008 Spring Meeting , 1069-D07-20 , 2007.
  38. Multiple Ion-Implanted GaN/AlGaN/GaN HEMTs with Remarkably Low Parasitic Source Resistance , K. Nomoto, M. Satoh and T. Nakamura , International Conference on Silicon Carbide and Related Materials 2007 , Th-207 , 2007.
  39. Double-ion-implanted GaN MESFETs with extremely low source/drain resistance , K. Nomoto, N. Itoh, T. Tajima, T. Kasai, T. Mishima, T. Inada, M. Satoh, and T. Nakamura , Mater. Res. Soc. Sympo. , Vol. 892, 0892-FF13-06.1 , 2006.
  40. Fabrication and electrical characteristics of Ti/Al ohmic contact to Si+ implanted GaN , N. Ito, A. Suzuki, M. Kawamura, K. Nomoto, T. Kasai, T. Mishima, T. Inada, T. Nakamura, M. Satoh , Mater. Res. Soc. Sympo. Proc. , Vol. 892, 0892-FF14-03.1 , 2006.
  41. Ion-Implanted GaN/AlGaN/GaN HEMTs with Extremely Low Gate Leakage Current Kazuki Nomoto, Tomoyoshi Mishima, Masataka Satoh and Tohru Nakamura , Mat. Res. Soc. Symp, 2006 Materials Research Society, 2006.
  42. Investigation of electrical properties in Si ion implanted GaN layer as a function of dose and energy, M. Satoh, T. Saitoh, K. Nomoto, and T. Nakamura, Mater. Res. Soc. Sympo. Proc, 955E, 0955-I15-31 , 2006.
  43. Fabrication and Electrical Characteristics of Ti/Al Ohmic Contact to Si implanted GaN , N. Ito, A. Suzuki, M.Kawamura, K.Nomoto, T.Kasai, T.Mishima, T. Inada, M. Satoh and T. Nakamura , Mat. Res. Soc. Symp Pro., 2005 Materials Research Society , 2005.
  44. Double Ion Implanted GaN MESFETs with Extrelely Low Source/Drain Resistance, K.Nomoto, N.Ito, T.Tajima, T.Kasai, T.Mishima, T. Inada, M. Satoh and T. Nakamura , Mat. Res. Soc. Symp Pro., 2005 Materials Research Society, 2005.
  45. Double Ion Implanted GaN MESFETs with Extrelely Low Source/Drain Resistance , K.Nomoto, N.Ito, T.Tajima, T.Kasai, T.Mishima, T. Inada, M. Satoh and T. Nakamura , MRS MEERING ABSTRACTS , 801 , 2005.
  46. Fabrication and Electrical Characteristics of Ti/Al Ohmic Contact to Si implanted GaN , N. Ito, A. Suzuki, M. Kawamura, K.Nomoto, T. Kasai, T. Mishima, T. Inada, M. Satoh and T. Nakamura , 2005MRS MEETING ABSTRACTS , 804 , 2005.
  47. Ti/Al-GaN Reaction Mechanism Forming Low Contact Resistivity , Y. Fukasawa, T. Nakamura, T. Nakamura , Mat. Res. Soc. Symp Pro. 2003 Materials Research Society , Vol. 743, pp. 795-799 , 2003.
  48. 1/f noise characteristics of sub-0.1micron CMOS for high-speed analog ULSI , T. Nakamura, M. Hase, K. Ohnishi, R. Tuchiya and T. Onai , 21st International Workshop on the Physics of Semiconductor Devices, IIT Madras, Chennai, India , 2003.
  49. Measurement of heat radiation from semiconductor equipment , A. Ohsawa,Tohru Nakamura, M. Satoh, T. Nakamura, J. Hata, Y. Kobayashi, T. Miyashita, M. Takahashi, M. Ohtani , SEMI Global Environment Symposium, Dec. 2003 , 2003.
  50. Direct Measurement of Heat Emission from a Semiconductor Equipment , A. Ohsawa, T. Nakamura, M. Satoh, T. Nakamura and J. Hata , The International Semiconductor Environment, Safety and Health(ISESH) conference 2003 , 2003.
  51. Ti/Al Interface Analysis for Low Contact Resistance formation , Y. Fukasawa, T. Nakamura, T. Nakamura , 2002MRS MEETING ABSTRACT , p. 297 , 2002.
  52. A 50nm CMOS Technology for High-Speed, Low-Power, and RF Application in 100nm node SoC Platform , K. Ohnishi, R. Tsuchiya, T. Yamauchi, F. Ootsuka, K. Mitsuda, M. Hase, T. Nakamura, T. Kawahara and T. Onai , 2001 International Electron Devices Meeting , pp. 227-230 , 2001.
  53. Advanced Performance of Small-Scaled InGaP/GaAs HBTs with fT over 150GHz and fmax over 250GHz, T.Oka, K. Hirata, K. Ouchi, H. Uchiyama, T. Taniguchi, and T. Nakamura, 1998 International Electron Devices Meeting, #25.1, 1998.
  54. High-speed InGaP/GaAs HBTs with Ballistic Transport in an Ultra-thin Base, (T. Oka, K. Ouchi, K. Mochizuki and T. Nakamura, 25th International Symposium on Compound Semiconductors, 1998.
  55. Cascode-Connected Dual-Gate InGaAs Pseudomorphic HEMT(CC-HEMT) for HighPower Amplifiers UsingSingle Voltage Supply(Invited Paper), T.Nakamura, T.Tanimoto, H. Matsumoto, I. Ohbu, S. Tanaka and N. Homma, 1996 Asia-Pacific Microwave Conference, 1996.
  56. New Technology of a Wsi Base Electrode anda Heavily-Doped Thin Base Layer for High-Performance InGaP/GaAsHBTs, T.Oka, K. Ouchi, K. Mochizuki, T. Tanoue and T. Nakamura, 1996 International Conference of SSDM, 1996.
  57. High Speed InGaP/GaAs HBTs with fmax of 159 GHz, T.Oka, K. Ouchi, K. Mochizuki, T. Tanoue and T.Nakamura, Topical Workshop on Heterostructure Microelectronics(TWHM ’96), 1996.
  58. Cascode-Connected GaAs E/D Dual Gate HEMTs(CC-HEMT) for L-Band High Power Amplifier, T. Tanimoto, I. Ohbu, A. Kawai, S. Tanaka and T. Nakamura, Topical Workshop on Heterostructure Microelectronics(TWHM ’96), 1996.
  59. Bipolar and BiCMOS on SOI(Invited), T.Nakamura, T. Shiba and T. Ikeda, 1996 3rd ECS Meeting for SOI, 1996.
  60. Test Structure and Experimental Analysis of Emitter-Base Reverse Voltage Stress Degradation in Self-Aligned Bipolar Transistors, H. Shimamoto, M. Tanabe, T. Onai, K. Washio and T. Nakamura, IEICE Transaction on Electronics vol. E79-C, No.2, pp. 211-218, 1996.
  61. High Efficiency Dual-Gate InGaAs Pseudomorphic HEMTs for High-Power AMP Using Single-Voltage Supply, I. Ohbu, T. Tanimoto, S. Tanaka, H. Matsumoto, A. Terano,M. Kudo and T. Nakamura, International Electron Devices Meeting, 1995.
  62. Single Voltage Supply High Efficiency InGaAs Pseudo-morphic Double Hetero HEMTs with Pt Buried Gates, T. Tanimoto, I. Ohbu, S. Tanaka, H. Matsumoto, A. Terano and T. Nakamura, 1995 International Conference of SSDM, 1995.
  63. Dual-Gate FETs for Ultra-High Efficiency HPA, T. Tanimoto, S. Tanaka, I. Ohbu, H. Matsumoto and T. Nakamura, 53rd Annual Device Research Conference, 1995.
  64. 47 GHz fT Si HBT with μC-Si Very Thin a-SiCx Double-Layer Emitter, M. Kondo, T. Shiba, Y. Tamaki and T. Nakamura, 5th International Symposium on Ultra Large Scale Integration Science & Technology, 1995.
  65. A New Optical Waveguide Structure-A Trench Channel-type High Density Waveguide in Si, T. Nakamura, T. Kato, T. Tanoue, F. Murai and M. Takeda, , SPIE Opto-electronic Interconnects III vol. 2400, pp. 94-99, 1995.
  66. GaInP/GaAs HBTs with Selectively Regrown Emitter and Widegap Extrinsic Base, S. L. Fu, S. Park, Y. M. Hsin, M. C. Ho, T. P. Chin, P. L. Yu,C. W. Tu, P. M. Asbeck and T. Nakamura, 52nd Annual Device Research Conference, 1994.
  67. InP/InGaAs Hetero-junction Bipolar Transistors with Regrown Emitters, H. Masuda, T. Tanoue, H. Kashima, T. Mochizuki and T. Nakamura, 6th International Conference on InP and Related Materials, 1994.
  68. An NPN 30 GHz, PNP 32 GHz fT ComplementaryBipolar Technology, (T. Onai, E. Ohue, Y. Idei, M. Tanabe, K. Washio and T. Nakamura, 1993 International Electron Devices Meeting, 1993.
  69. A 9.4μm2 38 GHz Sidewall Polycide Base Bipolar(SPOTEC)with Half-Micron CMOS Technology for Very-High-Speed ULSIs, T. Shiba, Y. Tamaki, T. Onai, M. Saitoh, T. Kure and T. Nakamura, IEEE 1993 Bipolar Circuits and Technology Meeting, 1993.
  70. AlGaAs/GaAs HBTs with Reduced Base-Collector Capacitance by Using Buried SiO2 and Poly-Crystalline GaAs in the Extrinsic Base and Collector, K. Mochizuki, T. Nakamura, T. Tanoue, H. Masuda and M. Horiuchi, 51st Annual Device Research Conference, 1993.
  71. Molecular Beam Deposition of Low-Resistance Poly-crystalline GaAs, K. Mochizuki, T. Nakamura, H. Masuda, T. Tanoue and M. Horiuchi, 1993 Electronic Material Conference, 1993.
  72. Sub-Quarter-Micron PMOSFETs with Shallow Source and Drain Formed by Rapid Vapor-Phase Doping(RVD), Y. Kiyota, T. Nakamura and T. Inada, 1993 Symposium on VLSI Technology, 1993.
  73. Bipolar and BiCMOS Devices and Circuitsfor ULSI, T. Nakamura, 183rd ECS Meeting vol. 93-1, 1993.
  74. Evaluation the Graft-Base Lateral Diffusion Depth of High-Performance Bipolar Transistor by Using Test Structure, Y. Tamaki, T. Shiba, T. Kure and T. Nakamura, 1993 International Conference on Microelectronics Test Structures, 1993.
  75. A Heterojunction Bipolar Transistor with an Epitaxially Regrown Emitter, T. Tanoue, H. Masuda, K. Washio and T. Nakamura, 1992 International Electron Devices Meeting, 1992.
  76. Novel Doping Process for Ultra-Shallow Junction: Rapid Vapor Phase Direct Doping, (Y. Kiyota, T. Onai, T. Nakamura, T. Inada, A. Kuranouchi and Y. Hirano, Material Research Society Spring Meeting 92, 1992.
  77. A 35 GHz 20μm2 Self-Aligned PNP Technology for Ultra-High-Speed High-Density Complementary Bipolar ULSIs, K. Washio, H. Shimamoto and T. Nakamura, 1992 Symposium on VLSI Technology, 1992.
  78. FRACS(Fully Radiative Current Path Structure)-A High Speed Bipolar Transistor with sub0.1μm Emitter, T. Onai, K. Nakazato, Y. Kiyota and T. Nakamura, 1992 Symposium on VLSI Technology, 1992.
  79. Test Structure and Experimental Analysis of Bipolar Hot-Carrier Degradation Including Stress Field Effect, H. Shimamoto, M. Tanabe, T,. Onai, K. Washio and T. Nakamura, 1992 International Conference on Microelectronics Test Structures, 1992.
  80. SOTEC-A Sub-10μm2Bipolar Transistor Structure Using Fully Self-aligned Sidewall Polycide Base Technology、T. Shiba, Y. Tamaki, T. Onai, M. Saito, T. Kure, F .Murai and T. Nakamura、1991 International Electron Devices Meeting、1991.
  81. A 64 GHz Si Bipolar Transistor Using In-Situ Phosphorus Doped Polysilicon Emitter Technology, M. Nanba, T. Kobayashi, T. Uchino, T. Nakamura, M. Kondo, Y. Tamaki, S. Iijima, T. Kure and M. Tanabe, 1991 International Electron Devices Meeting、1991.
  82. Ultra-small High-speed Bipolar Transistor with Sidewall Silicide Technology(Invited Paper), T. Nakamura, T. Onai, N. Homma, T. Shiba and Y. Tamaki, 1991 Bipolar Circuits and Technology Meeting, 1991.
  83. Rapid Vapor-Phase Direct Doping: Ultra-Shallow Junction Formation Methods fo rHigh-Speed Bipolar and Highly-Integrated DRAM LSIs, Y. Kiyota, T. Onai, T. Nakamura, T. Inada, A. Kuranouchi and Y. Hirano, 1991 International Conference of Solid State Device and Materials, 1991.
  84. An Ultra-High Emitter Efficiency Transistor with a Low-Temperature Processed Polysilicon Emitter for High-Speed Bipolar ULSI, M. Kondo, M. Nanbe, T. Kobayashi, S. Iijima and T. Nakamura, 1991 Symposium on VLSI Technology, 1991.
  85. Soft Error Immune 180um2 SICOS Upward Transistor Memory Cell Suitable for Ultra-high-speed High-density Memories, Y. Idei, T. Shiba, N. Homma, K. Yamaguchi, T. Nakamura, T. Onai, M. Namba, Y. Tamaki and Y. Sakurai, 1991 Symposium on VLSI Technology, 1991.
  86. Advanced Device Process Technology for0.3μm Self-Aligned Bipolar LSIs, Y. Tamaki, T. Shiba, T. Kure, K. Ohyu and T. Nakamura, 1990 Bipolar Circuits and Technology Meeting, 1990.
  87. 29 ps ECL Circuits Using U-Grooved Isolated SICOS Technology, T. Shiba, Y. Tamaki, I. Ogiwara, T. Kure, T. Kobayashi, K. Yagi, M. Tanabe and T. Nakamura, 1989 International Electron Devices Meeting, 1989.
  88. 1/5 Alpha-Ray-Induced Charge Reduction Using a New Trench Structure, T. Onai, T. Nakamura, K. Nakazato and N. Homma, 1989 Symposium on VLSI Technology, 1989.
  89. A 36 kb/2 ns RAM with1 kG/100 ps LogicGate Array, S. Isomura, A. Uchida, M. Iwabuchi, K. Ogiue, K. Matsumura, T. Nakamura and K. Yamaguchi, International Solid State Circuit Conference, 1989.
  90. Low Temperature Pseudo HBT Utilizing Bandgap Narrowing Effects, T. Yano, K. Nakazato, T. Onai, M. Aoki, K. Shimohigashi, T. Nakamura and T. Masuhara, 1998 International Conference on Solid State Devices and Materials, 1988.
  91. An Experimental Soft-error Immune64-kb 3ns ECL Bipolar RAM, K. Yamaguchi, H. Nanbu, K. Kanetani, N. Homma, T. Nakamura, K. Oohata, A. Uchida and K. Ogiue, Bipolar Circuits and Technology Meeting, 1988.
  92. Base Peripheral Effects on Future Self-aligned Bipolar devices for VLSIs, T. Shiba, Y. Tamaki, M. Nanba, K. Ikeda and T. Nakamura, Symposium on VLSI Technology, 1988.
  93. New Self-aligned Bipolar Device Process Technology for Sub50ps ECL Circuits, Y. Tamaki, T. Shiba, K. Ikeda, T. Nakamura S. Ohyu and T. Hayashida, Bipolar Circuits and Technology Meeting, 1987.
  94. Soft-Error Immune Switched-Load-Resistor Memory Cell, N. Homma, T. Nakamura, T. Hayashida, M. Matsumoto, K. Nakazato, T. Onai, T. Tamaki, M. Nanba, K. Sagara and K. Ikeda, Symposium on VLSI Technology, 1987.
  95. A 48 ps ECL in a Self-Aligned Bipolar Technology, K. Washio, T. Nakamura, K. Nakazato and T. Hayashida, 1987 International Solid-State Circuit Conference, 1987.
  96. 63 ps ECL Circuits Using Advanced SICOS Technology, T. Nakamura, K. Ikeda, K. Nakazato, K. Washio, M. Namba and T. Hayashida, 1986 International Electron Devices Meeting, 1986.
  97. A 3 GHz Lateral PNP Transistor, K. Nakazato, T. Nakamura and M. Kato, 1986 International Electron Devices Meeting, 1986.
  98. Ultra-High-Speed Bipolar Devices-SICOS(Invited Paper), T. Nakamura, K. Nakazato, K. Washio, Y. Tamaki, M. Nanba and T. Hayashida, 1986 International Conference of Solid State device and Materials, 1986.
  99. A New SICOS Schottky Devices, Y. Okada, T. Nakamura, T. Okabe and M. Nagata, 1985 International Electron Devices Meeting, 1985.
  100. A 6 GHz ECL Frequency Divider Using Sidewall Base Contact Structure, K. Nakazato, T. Nakamura, J-I Nakagawa, T. Okabe and M. Nagata, 1985 International Solid-State Circuit Conference, 1985.
  101. Degradation Analysis of Lateral PNP Transistor Exposed to X-Ray Irradiation, M. Kato, T. Nakamura, T. Toyabe, T. Okabe and M. Nagata, 1984 Annual Conference on Nuclear and Space Radiation Effects, 1984.
  102. Integrated 84 ps ECL with IIL, T. Nakamura, K. Nakazato, T. Miyazaki, T. Okabe and M. Nagata, 1984 International Solid-State Circuit Conference, 1984.
  103. 290 ps IIL Circuits with Five-Hold Self-Alignment, T. Nakamura, K. Nakazato, T. Miyazaki, M. Ogirima, T. Okabe and M. Nagata, 1982 International Electron Devices Meeting, 1982.
  104. SICOS - A High-Performance Bipolar Structure for VLSI, K. Nakazato, T. Nakamura, T. Miyazaki, T. Okabe and M. Nagata, 1982 Symposium on VLSI Technology, 1982.
  105. Self-Aligned Transistor with Sidewall Base Electrode, T. Nakamura, T. Miyazaki, S. Takahashi, T. Kure, T. Okabe and M. Nagata, 1981 International Solid-State Circuit Conference, 1981.
  106. Photo-current-Driven B-MOS without External Power Supply, T. Nakamura, T. Masuhara and S. Asai, 1977 9th Conference of Solid-State Devices, 1977.
  107. Back-Gate-Input MOS -A New Low Power Logic Concept, S. Asai, T. Masuhara and T. Nakamura, 1976 International Electron Devices Meeting, 1976.